The present invention relates in general to memory arrays and in particular to storing two bits for each data bit in a memory array.
Memory devices are typically provided as internal storage areas in the computer. There are several different types of memory. One type of memory is random access memory (RAM) that is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents.
A dynamic random access memory (DRAM) is a type of RAM. A DRAM memory is made up of memory cells. Each cell or bit includes a transistor and a capacitor. A cell is capable of storing information in the form of a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d bit as an electrical charge on the capacitor. Since a capacitor will lose its charge over time, a memory device incorporating a DRAM memory must include logic to refresh (recharge) the capacitors of the cells periodically or the information will be lost. Reading the stored data in a cell and then writing the data back into the cell at a predefined voltage level refreshes a cell. The required refreshing operation is what makes DRAM memory dynamic rather than static.
While a cell is being refreshed it cannot be read by a processor. This causes systems incorporating DRAMS to be slower than systems incorporating RAMS. However, DRAMS are more commonly used than RAMS because their circuitry is simpler and because they can hold up to four times as much data. Another disadvantage in using a typical DRAM is the amount of power needed to constantly refresh the cells. This disadvantage becomes more crucial as apparatuses incorporating memory devices are designed to use less and less power.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a DRAM memory device whose cells can go for an extended period of time without having to be refreshed
The above-mentioned problems with non-volatile memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a DRAM memory device having a folded architecture memory array of memory cells wherein, in a plan view, each memory cell has an area of 6F2 is disclosed. The DRAM memory device includes a plurality of pairs of associated memory cells to store data bits and a plurality of sense amplifiers. Each pair of associated memory cells includes a first memory cell to store a first bit and a second memory cell to store a second bit that is a complement of the first bit. The first bit and the second bit form a data bit. The plurality of sense amplifiers are used to read the memory cells. Each sense amplifier is coupled to an associated pair of memory cells. Moreover, each sense amplifier compares a voltage between the first bit of the first memory cell and the second bit of the second memory cell to read the data bit.
In another embodiment, a DRAM memory device having an open architecture memory array of memory cells wherein, in a plan view, each memory cell has an area of 6Fd. The DRAM memory device includes a plurality of pairs of associated memory cells to store data bits and a plurality of sense amplifiers. Each pair of associated memory cells includes a first memory cell to store a first bit and a second memory cell to store a second bit that is a complement of the first bit. The first bit and the second bit form a data bit. The plurality of sense amplifiers are used to read the memory cells. Each sense amplifier is coupled to an associated pair of memory cells. Moreover, each sense amplifier compares a voltage between the first bit of the first memory cell and the second bit of the second memory cell to read the data bit.
In another embodiment, a DRAM memory device includes a memory array having a plurality of memory cells arranged in a folded digit line architecture, a plurality of sense amplifiers, and a control logic circuit. Each memory cell has an area of 6F2 and each memory cell is associated with another memory cell, wherein each pair of associated memory cells store complementary bits that make up a data bit. The plurality of sense amplifiers are used to read and refresh memory cells. Each sense amplifier is coupled to a pair of associated memory cells. The control logic circuit is used to control memory operations. More specifically, the control circuit selectively fires word lines coupled to associated memory cells simultaneously so a sense amplifier coupled to the associated pair of memory cells can read and refresh the data bit stored in the pair of associated memory cells.
In another embodiment, a DRAM memory device includes a memory array having a plurality of memory cells arranged in an open digit line architecture, a plurality of sense amplifiers, and a control logic circuit. Each memory cell has an area of 6F2 and each memory cell is associated with another memory cell, wherein each pair of associated memory cells store complementary bits that make up a data bit. The plurality of sense amplifiers are used to read and refresh memory cells. Each sense amplifier is coupled to a pair of associated memory cells. The control logic circuit is used to control memory operations. More specifically, the control circuit selectively fires word lines coupled to associated memory cells simultaneously so a sense amplifier coupled to the associated pair of memory cells can read and refresh the data bit stored in the pair of associated memory cells.
In another embodiment, a memory system comprises a processor to provide external commands and a DRAM memory device. The DRAM memory device includes a memory array, sense amplifiers, and a control logic circuit. The memory array has memory cells arranged in a folded digit line architecture. Each memory cell has an area of 6F2 in a plane view. Moreover, each memory cell is associated with another memory cell, wherein each pair of associated memory cells store complementary bits to form a data bit. The sense amplifiers are used for each pair of associated memory cells to read data bits. Each sense amplifier is coupled to compare voltages of the bits in associated pairs of memory cells. The control circuit is used to receive external commands from the processor and to control memory operations. More specifically, the control circuit selectively fires word lines coupled to associated memory cells simultaneously to read a data bit.
In another embodiment, a memory system comprises a processor to provide external commands and a DRAM memory device. The DRAM memory device includes a memory array, sense amplifiers, and a control logic circuit. The memory array has memory cells arranged in an open digit line architecture. Each memory cell has an area of 6F2 in a plane view. Moreover, each memory cell is associated with another memory cell, wherein each pair of associated memory cells store complementary bits to form a data bit. The sense amplifiers are used for each pair of associated memory cells to read data bits. Each sense amplifier is coupled to compare voltages of the bits in associated pairs of memory cells. The control circuit is used to receive external commands from the processor and to control memory operations. More specifically, the control circuit selectively fires word lines coupled to associated memory cells simultaneously to read a data bit.
In another embodiment, a DRAM memory device having a folded architecture memory array of memory cells wherein, in a plan view, each memory cell having an area of less than 8F2 is disclosed. The DRAM memory device includes a plurality of pairs of associated memory cells to store data bits and a plurality of sense amplifiers. Each pair of associated memory cells includes a first memory cell to store a first bit and a second memory cell to store a second bit that is a complement of the first bit. The first bit and the second bit form a data bit. The plurality of sense amplifiers are used to read the memory cells. Each sense amplifier is coupled to an associated pair of memory cells. Moreover, each sense amplifier compares a voltage between the first bit of the first memory cell and the second bit of the second memory cell to read the data bit.
In another embodiment, a DRAM memory device having an open architecture memory array of memory cells wherein, in a plan view, each memory cell having an area of less than 8F2. The DRAM memory device includes a plurality of pairs of associated memory cells to store data bits and a plurality of sense amplifiers. Each pair of associated memory cells includes a first memory cell to store a first bit and a second memory cell to store a second bit that is a complement of the first bit. The first bit and the second bit form a data bit. The plurality of sense amplifiers are used to read the memory cells. Each sense amplifier is coupled to an associated pair of memory cells. Moreover, each sense amplifier compares a voltage between the first bit of the first memory cell and the second bit of the second memory cell to read the data bit.
In another embodiment, a method of operating a folded digit line DRAM memory array having a plurality of memory cells wherein, in a plan view, each memory cell has an area of 6F2 is disclosed. The method comprising, storing a first bit in a first memory cell, and storing a second bit that is complementary to the first bit in a second memory cell, wherein the first bit and the second bit form a data bit.
In another embodiment, a method of operating an open digit line DRAM memory array having a plurality of memory cells wherein, in a plan view, each memory cell has an area of 6F2 is disclosed. The method comprising, storing a first bit in a first memory cell, and storing a second bit that is complementary to the first bit in a second memory cell. Wherein the first bit and the second bit form a data bit.
In another embodiment, a method of operating a DRAM memory device having a memory array with multiple memory cells arranged in a folded digit line architecture wherein each memory cell has an area of 6F2 is disclosed. The method comprising, storing a charge in a first memory cell, and storing a complementary charge on an associated second memory cell, wherein the charge in the first memory cell and the complementary charge in the associated second memory cell together form a single data bit.
In another embodiment, a method of operating a DRAM memory device having a memory array with multiple memory cells arranged in an open digit line architecture wherein each memory cell has an area of 6F2 is disclosed. The method comprising, storing a charge in a first memory cell and storing a complementary charge on an associated second memory cell. Wherein the charge in the first memory cell and the complementary charge in the associated second memory cell together form a single data bit.
In another embodiment, a method of refreshing memory cells in a DRAM memory having a memory array of memory cells arranged in an folded digit line architecture wherein, in a plan view, each memory cell has an area of 6F2 is disclosed. The method comprising, storing a first bit in a first memory cell, storing a complementary second bit in an associated second memory cell, wherein the first bit and the complementary second bit form a data bit, comparing a voltage difference between the first bit in the first memory cell and the second bit in the second memory cell with a sense amplifier to read the data bit, restoring the first bit in the first memory cell to a predetermined voltage level, and restoring the second bit in the second memory cell to a predetermined voltage level.
In another embodiment, a method of refreshing memory cells in a DRAM memory having a memory array of memory cells arranged in an open digit line architecture wherein, in a plan view, each memory cell has an area of 6F2 is disclosed. The method comprising, storing a first bit in a first memory cell, storing a complementary second bit in an associated second memory cell, wherein the first bit and the complementary second bit form a data bit, comparing a voltage difference between the first bit in the first memory cell and the second bit in the second memory cell with a sense amplifier to read the data bit, restoring the first bit in the first memory cell to a predetermined voltage level, and restoring the second bit in the second memory cell to a predetermined voltage level.
In another embodiment, a method of operating a folded digit line DRAM memory array having a plurality of memory cells wherein, in a plan view, each memory cell has an area less than 8F2 is disclosed. The method comprising, storing a first bit in a first memory cell, and storing a second bit that is complementary to the first bit in a second memory cell, wherein the first bit and the second bit form a data bit.
In yet another embodiment, a method of operating an open digit line DRAM memory array having a plurality of memory cells wherein, in a plan view, each memory cell has an area of less than 8F2 is disclosed. The method comprising, storing a first bit in a first memory cell, and storing a second bit that is complementary to the first bit in a second memory cell. Wherein the first bit and the second bit form a data bit.